1. Field of the Invention
The invention generally relates to testing a plurality of memory devices in parallel and more specifically to increasing the level of parallelism in testing the memory devices.
2. Description of the Related Art
Testing is a critical step in the production of memory devices. Testing allows for defective products to be identified, repaired or removed from the supply chain, thereby ensuring that only the best quality products are delivered to customers. Testing may also expose design flaws and provide useful yield information which, when fed back into the fabrication process, can improve quality and efficiency of production. Therefore, it is highly desirable to perform testing and to acquire testing data at the earliest possible time.
Memory testing may comprise providing address signals, control signals for commands, power supply, and input/output (I/O) signals. Testing, for example, may involve performing a write operation. The write operation may be performed by first selecting an address location for the write operation by asserting the address along the address lines. The data to be written may then be provided along the data lines to write the data in the selected address location. Thereafter, a read operation may be performed at the address where the write was performed to verify that the data retrieved is indeed the data that was written. To perform the read operation, the address may be asserted again along the address lines and the data on the data lines may be captured. The control signals may be used to indicate the type of command being executed to facilitate communication between devices.
One solution to reducing total testing time and improving throughput is to simultaneously test multiple memory devices in parallel. FIG. 1 illustrates an exemplary parallel testing system 100. The system consists of a memory tester 101, a probe card 102 and one or more devices under test (DUT) 103. Dedicated lines flow from the memory tester 101 to the DUTs 103 through the probe card 102. As illustrated, sets of address, control, I/O, power and chip select lines flow from the memory tester 101 to a respective set of input ports 104 on probe card 102. Each set of input ports 104 is communicable coupled with a set of output ports 105. Each of output ports 105 is coupled with a respective DUT 103. With multiple address, control, I/O, power and chip select lines being provided, multiple devices may be tested in parallel. For example, in system 100 up to four devices may be simultaneously tested, thereby reducing testing time by a factor of four.
However, the increasing density and complexity of modern memory devices has meant longer test times per device and lower test throughput rates. Combating the increasing testing times has typically involved increasing the number of devices being tested in parallel. However, increasing the number of devices tested in parallel has meant increased pin counts and complexity of memory testers and probe cards. This in turn results in increased testing costs.
Therefore, what is needed are systems and methods for increasing the level of parallelism in memory testing in a more efficient manner.